Cross-couple gate structures are important for standard cell design to achieve product area scaling goals for logic and memory peripheral. For example, cross-coupling structures may be used to connect a p-type metal-oxide-semiconductor (pMOS) gate transistor and n-type MOS (nMOS) gate transistor with different gates in a logic cell. However, as technology node advances such as 14 nm technology nodes and beyond, lithography resolution is insufficient to print connected gates.
For example, middle of line (MOL) layers such as source/drain contacts (CA) and gate contacts (CB) can be used to cross couple gates. Such an approach for forming a cross-coupled logic cell is illustrated in FIGS. 1A and 1B (FIG. 1A is a top view and FIG. 1B is a generalized cross-sectional view). Adverting to FIG. 1A, active fins (or active layer) 101a and 101b and dummy fins 103a and 103b (to be eliminated) are formed with STI regions 105 therebetween. Gate structures 107, e.g., 107a-107e, are then formed across the active fins 101a and 101b, the dummy fins 103a and 103b, and the STI regions 105. Next, gate contacts 109 and S/D contacts 111 are formed on the gate structures 107a through 107e and active fins 101a and 101b, respectively. Thereafter, portions of gate structures 107b and 107c are cut out between the active or dummy fins 103a and 103b, e.g., by double patterning, to form the gate cut region 113. Consequently, the neighboring pMOS formed by active fins 101a and the nMOS formed by active fins 101b along the same gate are disconnected.
Adverting to FIG. 1B, gate structures 107 are formed on a substrate 121, the substrate 121 having silicide or salicide portions 123. Next, gate contacts 109 and S/D contacts 111 are formed on the gate structures 107 and the silicide portions 123, respectively. A metal layer 125 is then formed on top of the gate contacts 109 and S/D contacts 111, respectively. As shown, gate contacts 109 and S/D contacts 111 are formed on the same level. Consequently, as shown by the arrows in FIG. 1A, tight spacing among the S/D contacts 111 and 115 and gate contacts 109 causes considerable congestion, which in turn reduces overall design flexibility.
A need therefore exists for methodology enabling cross coupling of disconnected gates in advanced logic cells while mitigating design congestion.